The present invention is related to an image processing apparatus, and more particularly to a game computer which displays image data by an interlace displaying system.
In a conventional image processing apparatus, two kinds of displaying systems, that is, an interlace system and a non-interlace system, are used to display image data. Generally, the interlace displaying system is used for TVs of an NTSC (National Television System Committee) System, and the non-interlace displaying system is used for computer image processors.
According to the interlace displaying system, 525 scanning lines are divided into odd fields and even fields, and the two kinds of fields are scanned alternately so that the image is displayed clearly by an "after-image" phenomenon. For that reason, the interlace displaying system is suited for the TV image generally which includes a natural picture, moving at long intervals.
According to the non-interlace displaying system for RGB data, 263 scanning lines of the even fields or 262 scanning lines of the odd fields are selectively used. Image data are supplied to a VRAM (Video RAM) during a horizontal fly-back time, and then the image data are transmitted through a video encoder to a display device in accordance with a predetermined synchronizing signal.
The computer image processor treats both still and moving pictures. In such a processor, if the moving picture acting at shorter intervals is displayed by the interlace system, the displayed image has many notches at the edge thereof. Further, the interlace system needs information approximately twice that of the non-interlace system to display the same image. The image data must be transmitted and processed with exact timing to display the image in the interlace display mode.
Process periods of a variety of image data are different from each other depending on the data form and amount, so that output timings of the image data necessarily are different from each other as well. Therefore, the transmission periods of the image data must be adjusted precisely when a variety of image are superimposed, that is, the CPU must control each peripheral devices with exact timing. According to the conventional computer, however, it is difficult to control the peripheral devices with exact timing because the image data are transmitted in synchronization with vertical synchronizing signals.